Semiconductor device electrodes are generally coupled to semiconductor device active regions through openings exposing the active regions. As these active regions and devices in general are appreciably scaled, it is necessary that the electrode openings exposing the active regions of the devices and the electrodes themselves are also scaled accordingly. If the openings and electrodes are not scaled down, many real estate and performance advantages obtained by smaller devices will be sacrificed due to large electrode size.
Electrode openings that expose the active regions of a semiconductor device are typically formed by photolithographic processes that are well known in the art. By employing these practical photolithographic processes, it is possible to create openings having widths as small as 0.5 microns through which active regions may be contacted. Additionally, a margin for error must always be allowed as with all photolithographic processes. In order to fabricate openings and electrodes having dimensions smaller than 0.5 microns and less margin for error, technology other than photolithography as is currently practical must be developed.
Accordingly it would be highly desirable to have a method of fabricating semiconductor device electrodes that would create electrodes independent of lithography resolution tolerances and smaller than those attainable using standard photolithographic processes.